Triple well transmit-receive switch transistor

ABSTRACT

A transistor arrangement including a triple well structure, the triple well structure including a substrate of a first conductivity type, a first well region of a second conductivity type formed within the substrate and a second well region of the first conductivity type being separated from the substrate by the first well region. The transistor arrangement further includes a first transistor formed on or in the second well region, the first transistor including a body terminal being connected to the second well region and a second well region switch being connected to the body terminal of the first transistor.

FIELD OF THE INVENTION

The present invention relates to the field of transmit-receive (T/R)switches, and in particular, to a T/R switch design with low insertionloss, high isolation, high linearity and high power handling capability.

BACKGROUND OF THE INVENTION

With the development of modern silicon technology, more and morehigh-frequency circuits can be implemented in standard CMOS process.Radio-frequency (RF) integrated circuits (IC) in standard CMOStechnology have proven feasible. However, further integration of T/Rantenna switches in CMOS is quite challenging due to the higher loss ofsilicon substrate and lower linearity of CMOS devices.

For years RF switch has been dominated by discrete components usingp-type, intrinsic, n-type (PIN) diodes and III-V metal-semiconductorfield-effect transistors (MESFETs). Recently, CMOS T/R switch design hasbeen explored to a certain extent. In relation to insertion loss,publication “A 0.5-μm CMOS T/R Switch for 900-MHz WirelessApplications”, Huang F. J. et al, IEEE Journal of Solid-State Circuits,Vol. 36 No. 3, pp. 486-492, March 2001 and publication “5.8-GHz CMOS T/RSwitches With High and Low Substrate Resistances in a 0.18-μm CMOSProcess”, Li Z. B. et al, IEEE Microwave and Wireless ComponentsLetters, Vol. 13, No. 1, pp. 1-3, January 2003 reported that lowinsertion loss can be achieved by optimizing the transistor widths andbias voltages, by minimizing the substrate resistances, and by dcbiasing the transmit and receive nodes, which decreases the capacitanceswhile increasing the power 1-dB compression point.

In relation to isolation, publication “A High-performance CMOS-SOIAntenna Switch for the 2.5-5-GHz’, Carlo Tinella et al, IEEE Journal ofSolid-State Circuits, Vol. 38, No. 7, pp. 1279-1283, July 2003 reportedthat a high isolation can be achieved by taking advantage of the highresistive substrate and underlying oxide of silicon-on-insulator (SOI)technology. However, in these respective publications, linearity waslimited due to parasitic capacitance and source-drain junction diodes.Thus various techniques are developed to achieve higher linearity.

One technique to increase linearity is the body floating technique.Publication “Integrated CMOS Transmit-Receive Switch Using LC_tunedSubstrate Bias for 2.4-GHz and 5.2-GHz Applications”, Niranjan A.Talwalkar et al, IEEE Journal of Solid-State Circuits, Vol. 39, No. 6,pp. 863-870, June 2004 introduced a body floating technique involving aninductive substrate bias scheme. The bias scheme uses aninductor-capacitor (L/C) tank to enhance the linearity of the metaloxide semiconductor field-effect transistor (MOSFET) when used as a passgate at RF. However, this technique has the disadvantages of designcomplexity and consumption of large silicon area.

Taking advantage of triple-well CMOS process, another body floatingtechnique can be realized using a large resistor to bias the body orbulk as reported in publication “Design and Analysis for a MiniatureCMOS SPDT Switch Using Body-Floating Technique to improve PowerPerformance”, Yeh M. C et al, IEEE Transactions on Microwave Theory andTechniques”, Vol. 54, No. 1, pp. 31-39, January 2006. As resistors areintrinsically wideband, the linearity improvement of this technique isalso wideband.

Another technique to improve linearity involves the use of stackedtransistors. Publication “21.5-dBm Power-Handling 5-GHz Transmit/ReceiveCMOS Switch Realized by Voltage Division Effect of Stacked TransistorConfiguration With Depletion-Layer-Extended Transistors (DETs), TakahiroOhnakado et al, IEEE Journal of Solid-State Circuits, Vol. 39, No. 4,pp. 577-584, April 2004 reported a T/R CMOS switch utilizing thedepletion-layer-extended transistor (DET), which possesses higheffective substrate resistance and enables the voltage division effectof the stacked transistor configuration to work in the CMOS switch.Although linearity is improved, insertion loss will be degraded and hasto be compensated by the DET.

Yet another technique to improve linearity involves integration ofon-chip LC impedance transformation networks (ITNs) into a switch.Publication “15-GHz Fully Integrated nMOS Switches in a 0.13-μm CMOSProcess” reported two fully integrated nMOS switches which have beendemonstrated at 15 GHz in a 0.13-m CMOS foundry process. One switchincorporates on-chip LC ITNs while the second switch does not. Theswitches with and without ITNs achieve the same 1.8-dB insertion loss at15 GHz, but 21.5 and 15 dBm input P_(1dB), respectively. The degradationof insertion loss due to use of ITNs is compensated by reducing themismatch loss caused by the bond pad parasitics. The switch without ITNsis suitable for 3.1-10.6 GHz ultra-wide-band (UWB) applications. Theswitch with ITNs has 5 dB worse isolation than the switch without. Thedifference is due to the larger transistor size of the switch with ITNs,which introduces lower parasitic impedance path between Tx/Rx ports andantenna port. In this publication, although linearity is improved,isolation performance is degraded.

Yet another technique to improve linearity involves the use ofdifferential architectures. Publication “A Differential CMOS T/R Switchfor Multistandard Applications”, Zhang Y. P. et al, IEEE Transactions onCircuits and Systems-II: Express Briefs, Vol. 53, No. 8, pp. 782-786,August 2006 presented a differential T/R switch integrated in a 0.18-mstandard CMOS technology for wireless applications up to 6 GHz. Thisswitch design employs a fully differential architecture to accommodatethe design challenge of differential transceivers and improve thelinearity performance. It exhibits less than 2-dB insertion loss, higherthan 15-dB isolation, in a 60 m×40 m area. 15-dBm power at 1-dBcompression point (1 dB) is achieved without using additional techniquesto enhance the linearity. This switch is suitable for differentialtransceiver front-ends with a moderate power level.

Comparing to other RF IC circuits that have been pushed up to 60-GHz,the current design of CMOS T/R switches for higher frequency operationsare explored only to a limited extent. Most of these switches adoptseries-shunt architecture. At higher frequencies, the loss due to theshunt arm will severely degrades the insertion loss, while the lack ofshunt arm will result in low isolation. Therefore, an objective of thepresent invention is to provide an alternative T/R switch design withlow insertion loss, high isolation, high linearity and high powerhandling capability thereby advantageously avoids or reduces some of theabove-mentioned drawbacks of prior art devices.

SUMMARY OF THE INVENTION

In one embodiment of the invention, a transistor arrangement is providedincluding a triple well structure, the triple well structure including asubstrate of a first conductivity type, a first well region of a secondconductivity type formed within the substrate and a second well regionof the first conductivity type being separated from the substrate by thefirst well region. The transistor arrangement further includes a firsttransistor formed on or in the second well region, the first transistorincluding a body terminal being connected to the second well region anda second well region switch being connected to the body terminal of thefirst transistor.

In one embodiment of the invention, a controller may be connected to acontrol terminal of the second well region switch and control the secondwell region switch to be opened when the first transistor is in the ONstate and to be closed when the first transistor is in the OFF state.The controller may be an input source supplying a drive voltage to thegate terminal in the case of a MOSFET transistor or to the base terminalin the case of a BJT transistor. The drive voltage or voltage appliedbetween gate and source (or between base and emitter of a BJT) to switchthe MOSFET ON must exceed a threshold value V_(T). Reducing the drivevoltage to below V_(T) will cause the MOSFET to turn OFF.

In another embodiment of the invention, the substrate may be a P-typesubstrate, the first well region may be an N-type well region and thesecond well region may be a P-type well region for an NMOS transistor.For a PMOS transistor, the substrate may be an N-type substrate, thefirst well region may be a P-type well region and the second well regionmay be an N-type well region.

In a further embodiment of the invention, the first transistor furtherincludes a source terminal, a gate terminal and a drain terminal inaddition to a body terminal. The source terminal includes a sourcediffusion region of the second conductivity type being formed in thesecond well region and the drain terminal including a drain diffusionregion of the second conductivity type being formed in the second wellregion. The body terminal includes a body diffusion region of the firstconductivity type being formed in the second well region. The sourceterminal and the drain terminal include a diffusion region of adifferent conductivity from the body terminal. The source terminal, thedrain terminal and the body terminal include diffusion regions formed inthe second well region.

In another embodiment of the invention, the second well region switchmay be a transistor. The transistor may be a field-effect transistor ora bipolar transistor. The transistor may be selected from a group oftransistors consisting of metal-oxide-semiconductor field-effecttransistor, n-channel metal-oxide-semiconductor field-effect transistor,p-channel metal-oxide-semiconductor field-effect transistor, junctiongate field-effect transistor, insulated gate bipolar transistor but notso limited.

In another embodiment of the invention, a first well region terminal maybe connected to the first well region. The first well region terminalconnected to the first well region may include a diffusion region of thesecond conductivity type being formed in the first well region.

In another embodiment of the invention, a passive component may becoupled to the first well region terminal. The passive component mayinclude a component selected from the group consisting of resistor,inductor and capacitor. Alternatively, a first well region switch may becoupled to the first well region terminal. The first well region switchmay be a transistor. The transistor may be a field-effect transistor ora bipolar transistor. The transistor may be selected from a group oftransistors consisting of metal-oxide-semiconductor field-effecttransistor, n-channel metal-oxide-semiconductor field-effect transistor,p-channel metal-oxide-semiconductor field-effect transistor, junctiongate field-effect transistor, insulated gate bipolar transistor but notso limited.

In another embodiment of the invention, the transistor arrangement mayhave a single-ended architecture or a differential architecture.

In another embodiment of the invention, the transistor arrangement mayinclude a second transistor having a source terminal, a gate terminaland a drain terminal. The gate terminal of the first transistor and thegate terminal of the second transistor may be arranged at a distancefrom one another of at least about twice the maximum process technologyresolution.

In one embodiment of the invention, a transistor arrangement is providedincluding a triple well structure, the triple well structure including asubstrate of a first conductivity type, a first well region of a secondconductivity type formed within the substrate and a second well regionof the first conductivity type being separated from the substrate by thefirst well region. The transistor arrangement further includes a firsttransistor formed on or in the second well region and the firsttransistor including a body terminal being connected to the second wellregion. The transistor arrangement also includes a first passivecomponent being connected to the body terminal of the first transistor,a first well region terminal connected to the first well region and asecond passive component being coupled to the first well regionterminal.

In one embodiment of the invention, a transistor arrangement is providedincluding a triple well structure, the triple well structure including asubstrate of a first conductivity type, a first well region of a secondconductivity type formed within the substrate and a second well regionof the first conductivity type being separated from the substrate by thefirst well region. The transistor arrangement further includes a firsttransistor formed on or in the second well region and the firsttransistor including a body terminal being connected to the second wellregion. The transistor arrangement also includes a second well regionswitch being connected to the body terminal of the first transistor, afirst well region terminal connected to the first well region and afirst passive component being coupled to the first well region terminal.

The following figures illustrate various exemplary embodiments of thepresent invention. However, it should be noted that the presentinvention is not limited to the exemplary embodiments illustrated in thefollowing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a cross-sectional view of a transistor arrangementincluding a first NMOS transistor in a triple-well structure with thebody terminal being biased by a second NMOS transistor according to anembodiment of the present invention;

FIG. 1B shows a cross-sectional view of a transistor arrangementincluding an NMOS transistor in a triple-well structure with the bodyterminal being biased by a PMOS transistor according to an embodiment ofthe present invention;

FIG. 2 shows a cross-sectional view of a transistor arrangementincluding an NMOS transistor in a triple-well structure with the bodyterminal being biased by a first resistor and the N-well terminal beingbiased by a second resistor according to an embodiment of the presentinvention;

FIG. 3A shows a cross-sectional view of a transistor arrangementincluding a first NMOS transistor in a triple-well structure with thebody terminal being biased by a second NMOS transistor and the N-wellterminal being biased by a resistor according to an embodiment of thepresent invention;

FIG. 3B shows a cross-sectional view of a transistor arrangementincluding an NMOS transistor in a triple-well structure with the bodyterminal being biased by a PMOS transistor and the N-well terminal beingbiased by a resistor according to an embodiment of the presentinvention;

FIG. 4A shows a cross-sectional view of a transistor arrangementincluding a first NMOS transistor in a triple-well structure with thebody terminal being biased by a resistor and the N-well terminal beingbiased by a second NMOS transistor according to an embodiment of thepresent invention;

FIG. 4B shows a cross-sectional view of a transistor arrangementincluding an NMOS transistor in a triple-well structure with the bodyterminal being biased by a resistor and the N-well terminal being biasedby a PMOS transistor according to an embodiment of the presentinvention;

FIG. 5A shows a cross-sectional view of a transistor arrangementincluding a first NMOS transistor in a triple-well structure with thebody terminal being biased by a second NMOS transistor and the N-wellterminal being biased by a third NMOS transistor according to anembodiment of the present invention;

FIG. 5B shows a cross-sectional view of a transistor arrangementincluding an NMOS transistor in a triple-well structure with the bodyterminal being biased by a first PMOS transistor and the N-well terminalbeing biased by a second PMOS transistor according to an embodiment ofthe present invention;

FIG. 6 shows a schematic of a conventional series-shunt typesingle-ended T/R switch arrangement;

FIG. 7 shows a model of parasitic capacitances of a MOS transistor thatis used as a switch when the transistor is in the cut-off region;

FIG. 8 shows a layout sketch of an interdigitized MOS transistor used asa switch;

FIG. 9A shows a foundry p-cell layout of an NMOS transistor operating asa switch;

FIG. 9B shows a customized layout of an NMOS transistor operating as aswitch according to an embodiment of the present invention;

FIG. 9C shows a comparison table of parasitic capacitances of an NMOStransistor in cutoff region based on a p-cell foundry layout and acustomized layout according to an embodiment of the present invention;

FIG. 10 shows a graph of simulated insertion loss and isolation of a T/Rswitch with and without shunt arms according to an embodiment of thepresent invention;

FIG. 11 shows a graph of simulated linearity of a T/R switch with andwithout shunt arms, and with different types of body-floating accordingto an embodiment of the present invention;

FIG. 12 shows a graph of simulated insertion loss and isolation of a T/Rswitch without shunt arms, and with and without body-floating accordingto an embodiment of the present invention;

FIG. 13 shows a schematic of a differential T/R switch arrangementaccording to an embodiment of the present invention;

FIG. 14 shows a die photograph of fabricated differential T/R switchaccording to an embodiment of the present invention;

FIG. 15 shows a graph of measured insertion loss and isolation fordifferential-mode small-signals according to an embodiment of thepresent invention;

FIG. 16 shows a graph of measured common-mode rejection ratio in the ONand OFF mode of the differential T/R switch according to an embodimentof the present invention;

FIG. 17 shows a graph of power handling capability in terms of P_(1dB)at different frequencies according to an embodiment of the presentinvention;

DETAILED DESCRIPTION OF THE INVENTION

Exemplary embodiments of a switch transistor arrangement are describedin details below with reference to the accompanying figures. Inaddition, the exemplary embodiments described below can be modified invarious aspects without changing the essence of the invention.

FIG. 1A shows a cross-sectional view of a transistor arrangement or aT/R switch arrangement including a first NMOS transistor in atriple-well structure with the body terminal being biased by a secondNMOS transistor according to an embodiment of the present invention. Thetransistor arrangement 100 includes a triple well structure 102 and afirst NMOS transistor 104 formed on or in a P-type well 106 of thetriple well structure 102. The triple well structure 102 includes theP-type well 106, an N-type well 108 and a P-type substrate 110. TheP-type well 106 and the N-type well 108 are located inside the P-typesubstrate 110 and the N-type well 108 isolates the P-type well 106 fromthe P-type substrate 110. The P-type substrate 110 is typically P-typesilicon, for example having a resistivity range of about 10 ohm-cm toabout 25 ohm-cm. The P-type well 106 or P-well has a typical well depthof, for example, about 2 μm to about 4 μm with an average dopingconcentration, for example, in the range of about 1×10¹⁶ atoms per cubiccentimeter to about 5×10¹⁶ atoms per cubic centimeter. The N-type well108 or N-well has a typical well depth of, for example, about 4 μm toabout 8 μm. The doping concentration may be from about 4×10¹⁵ atoms percubic centimeter to about 1×10¹⁶ atoms per cubic centimeter. The triplewell structure 102 is formed by the P-type well 106 counter doping theN-type well 108. The formation of the elements in the triple wellstructure 102 is as follows. An N-type well 108 implant is done, forexample, with phosphorous (P₃₁) with a typical dose of about 1.0 atomsper square centimeter to about 1.5×1013 atoms per square centimeter andenergies from about 160 Kev to about 100 Kev. The N-type well 108implant is driven using a high temperature step which may typically beabout 6 to about 12 hours at about 1125° C. to about 1150° C. The N-typewell 108 is then counter doped with a P-type well 106 implant. Typicaldosages for the P-type well 106 implant could be about 1.5 atoms persquare centimeter to about 2.5×1013 atoms per square centimeter withenergies of about 30 Kev to about 180 Kev using a species such as boron(B₁₁). The N-type well 108 and P-type well 106 are then driven,typically about 6 hours to about 10 hours at about 1125° C. to about1150° C. This sets the respective P-type 106 and N-type 108 wells to thedesired doping concentrations and depths.

The first NMOS transistor 104 includes a body terminal 112 having aP-type body diffusion region 114, a source terminal 116 having an N-typesource diffusion region 118, a drain terminal 120 having an N-type draindiffusion region 122 and a gate terminal 124. The P-type body diffusionregion 114, the N-type source diffusion region 118 and the N-type draindiffusion region 122 are all formed in the P-type well 106. Thetransistor arrangement 100 further includes a second NMOS transistor 126which acts as a switch and is connected to the body terminal 112 of thefirst NMOS transistor 104 so as to bias the first NMOS transistor 104such that the body terminal 112 of the first NMOS transistor 104 isfloating only when the first NMOS transistor 104 is in the ON state. Thebody terminal 112 of the first NMOS transistor 104 is not floating whenthe first NMOS transistor 104 is in the OFF state. By turning on thebody floating only when the first NMOS transistor 104 is in the ON statemay further improve the isolation performance of the transistorarrangement. The second NMOS transistor 126 includes a body terminal(not shown), a source terminal 128, a drain terminal 130 and a gateterminal 132. The drain terminal 130 of the second NMOS transistor 126is connected to the body terminal 112 of the first NMOS transistor 104and the source terminal 128 of the second NMOS transistor 126 isconnected to ground. To turn the second NMOS transistor 1260N, a voltageis applied to the gate terminal 132 of the second NMOS transistor 126such that the gate-source voltage is above the threshold voltage of thetransistor. The second NMOS transistor 126 will be OFF if thegate-source voltage drops below the threshold voltage of the transistor.The transistor arrangement 100 further includes an N-well terminal 134connected to the N-type well 108. The N-well terminal 134 includes anN-type diffusion region 136 formed in the N-type well 108. Thetransistor arrangement 100 also includes a P-substrate terminal 138connected to the P-type substrate 110. The P-substrate terminal 138includes a P-type diffusion region 140 formed in the P-type substrate110.

The body terminal of the first NMOS transistor can also be biased by aPMOS transistor. FIG. 1B shows a cross-sectional view of a transistorarrangement including an NMOS transistor in a triple-well structure withthe body terminal being biased by a PMOS transistor according to anembodiment of the present invention. Features already described withrespect to FIG. 1A will not be described again here. Nevertheless, samereference signs refer to identical components. The PMOS transistor 142includes a body terminal (not shown), a source terminal 144, a drainterminal 146 and a gate terminal 148. The drain terminal 146 of the PMOStransistor 142 is connected to the body terminal 112 of the NMOStransistor 104 and the source terminal 144 of the PMOS transistor 142 isconnected to a power supply V_(DD). To turn the PMOS transistor 1420N, avoltage is applied to the gate terminal 148 of the PMOS transistor 142such that the gate-source voltage is below the threshold voltage of thetransistor. The PMOS transistor 142 will be OFF if the gate-sourcevoltage increases above the threshold voltage of the transistor.

FIG. 2 shows a cross-sectional view of a transistor arrangementincluding an NMOS transistor in a triple-well structure with the bodyterminal being biased by a first resistor and the N-well terminal beingbiased by a second resistor according to an embodiment of the presentinvention. The presence of an N-type well 108 in the triple wellstructure 102 creates two more diodes, namely the diode 150 between theP-type well 106 and the N-type well 108 and the diode 152 between theN-type well 108 and the P-type substrate 110. The body terminal 112 ofthe NMOS transistor 104 is biased by a large resistor 154 thereby thebody terminal 112 becomes RF floating. When the body terminal 112 of theNMOS transistor 104 is floated by a large resistor 154, the transientvoltage of the P-type well 106 is actually bootstrapped by the signalvoltage. This prevents the source-bulk diode 156 and drain-bulk diode158 from being turned on by large signals and thereby improve thelinearity performance of the transistor arrangement. However, the diode150 between the P-type well 106 and the N-type well 108 becomesunprotected and can be turned on by large P-type well 106 voltages. Oncethe turn-on happens, the RF-floating state of the body terminal 112 inthe P-type well 106 is broken and the linearity performance may bedegraded immediately. To overcome the body-floating limitation, adouble-well body-floating technique is introduced where both the P-typewell 106 and the N-type well 108 are biased by large resistors 154, 160.With both the body terminal 112 of the P-type well 106 and the N-wellterminal 134 of the N-type well 108 floated, the diode 150 between theP-type well 106 and the N-type well 108 and the diode 152 between theN-type well 108 and P-type substrate 110 will not be turned on andlinearity performance of the transistor arrangement will not bedegraded.

FIG. 3A shows a cross-sectional view of a transistor arrangementincluding a first NMOS transistor in triple-well technology with thebody terminal being biased by a second NMOS transistor and the N-wellterminal being biased by a resistor according to an embodiment of thepresent invention. FIG. 3A is similar to FIG. 1A except that the N-wellterminal 134 has been biased by a resistor 160 as shown in FIG. 3A.Biasing the body terminal 112 of the first NMOS transistor 104 with asecond NMOS transistor 126 enables body-floating condition only when thefirst NMOS transistor 104 is ON, thereby improving the isolationperformance while biasing the N-well terminal 134 with a resistor 160may help to overcome the body-floating limitation due to the diode 150between the P-type well 106 and the N-type well 108 and the diode 152between the N-type well 108 and P-type substrate 110.

FIG. 3B shows a cross-sectional view of a transistor arrangementincluding an NMOS transistor in a triple-well structure with the bodyterminal being biased by a PMOS transistor and the N-well terminal beingbiased by a resistor according to an embodiment of the presentinvention. FIG. 3B is similar to FIG. 3A with the difference such thatthe body terminal 112 of the NMOS transistor 104 is biased by a PMOStransistor 142 instead of an NMOS transistor.

FIG. 4A shows a cross-sectional view of a transistor arrangementincluding a first NMOS transistor in a triple-well structure with thebody terminal being biased by a resistor and the N-well terminal beingbiased by a second NMOS transistor according to an embodiment of thepresent invention. FIG. 4A is similar to FIG. 2 except that the N-wellterminal 134 has been biased by a NMOS transistor 162 as shown in FIG.4A instead of a resistor.

FIG. 4B shows a cross-sectional view of a transistor arrangementincluding an NMOS transistor in a triple-well structure with the bodyterminal being biased by a resistor and the N-well terminal being biasedby a PMOS transistor according to an embodiment of the presentinvention. FIG. 4B is similar to FIG. 4A with the difference such thatthe N-well terminal 134 is biased by a PMOS transistor 164 as shown inFIG. 4B instead of an NMOS transistor.

FIG. 5A shows a cross-sectional view of a transistor arrangementincluding a first NMOS transistor in a triple-well structure with thebody terminal being biased by a second NMOS transistor and the N-wellterminal being biased by a third NMOS transistor according to anembodiment of the present invention. FIG. 5A is similar to FIG. 3A withthe difference such that the N-well terminal 134 is biased by an NMOStransistor 162 instead of a resistor. Biasing the N-well terminal 134 byan NMOS transistor 162 instead of a resistor allows the flexibility ofsynchronizing with the NMOS transistor which is connected to the bodyterminal.

FIG. 5B shows a cross-sectional view of a transistor arrangementincluding an NMOS transistor in a triple-well structure with the bodyterminal being biased by a first PMOS transistor and the N-well terminalbeing biased by a second PMOS transistor according to an embodiment ofthe present invention. FIG. 5B is similar to FIG. 5A with the differencesuch that the body terminal 112 of the NMOS transistor 104 and theN-well terminal 134 are respectively biased by PMOS transistors 142, 164instead of NMOS transistors.

FIG. 6 shows a schematic of a conventional series-shunt typesingle-ended T/R switch arrangement. The T/R switch arrangement 166includes two series 168 and two shunt 170 transistors. The seriestransistors 168, M1 and M2, perform the main switching functions for thetransmit (TX) and receive (RX) paths and the shunt transistors 170, M3and M4, increase the isolation of the switch. The shunt transistors 170,M3 and M4, are turned ON when the series transistors 168, M1 and M2 areturned OFF respectively, so that the undesired signal in each mode canbe grounded by the shunt transistors 170. A shunt transistor may improveisolation but as a tradeoff, degradation on the insertion loss isobserved, which may result from the parasitic capacitances of the shunttransistors in the cutoff region. Each of the shunt 170 or series 168transistors includes a body terminal (not shown), a source terminal, adrain terminal and a gate terminal. The source terminal of thetransistor M1 is connected to the transmitter (TX) and to the drainterminal of the transistor M3, the gate terminal is connected to one endof a gate bias resistor R_(G1) and the drain terminal is connected to anantenna (ANT) and to the source terminal of the transistor M2. The gateterminal of the transistor M2 is connected to one end of another gatebias resistor R_(G2) and the drain terminal is connected to the receiver(RX) and to the drain terminal of transistor M4. The gate terminal oftransistor M3 is connected to one end of gate bias resistor R_(G3) andthe source terminal is connected to ground. The gate terminal oftransistor M4 is connected to one end of gate bias resistor R_(G4) andthe source terminal is connected to ground. The other end of each of therespective gate bias resistors R_(G1), R_(G2), R_(G3), R_(G4) isconnected to a power supply. The gate bias resistors may serve toimprove dc-bias isolation.

FIG. 7 shows a model of parasitic capacitances of a MOS transistor thatis used as a switch when the transistor is in the cut-off orsubthreshold region where the transistor is turned OFF, and there is noconduction between drain and source. The OFF resistance between thedrain and the source is very large and normally not considered. Theparasitic capacitances couple part of the signal to ground and lead toinsertion loss degradation. As the channel of the MOS transistor is notformed, gate-source capacitance (C_(gs)) and gate-drain capacitance(C_(gd)) are due only to overlap and fringing capacitances.

C_(gs)=C_(gd)WL_(ov)C_(ox)  (1)

where L_(ov) denotes the overlap distance between gate and source/drain,C_(ox) denotes the gate capacitance per unit area,W is the width of transistor.

The values of C_(gs) and C_(gd) may be very small when compared to thatof a MOS transistor in saturation or triode region. The values ofsource-bulk capacitance (C_(sb)) and drain-bulk capacitance (C_(db)) mayalso be small when the channel is not present. The values of C_(sb) andC_(db) depend on the area of source and drain, respectively. For astand-alone MOS transistor, drain-source capacitance (C_(ds)) may bevery small and is normally not considered. However, when the transistoris used as a switch, the metal connection style exhibits severe couplingbetween drain and source, and thus C_(ds) can not be ignored. This canbe explained by a layout sketch of an interdigitized MOS transistor.

FIG. 8 shows a layout sketch of an interdigitized MOS transistor used asa switch according to an embodiment of the present invention. The metalconnections of the drain 172 and the source 174 are in parallel and nextto each other. When these metals are connected as a switch, theyactually form a lateral metal capacitor, which is of high capacity. Theeffect becomes more significant with the scale down of technologies, asthe metal distance between drain 172 and source 174 decreases withsmaller channel length.

FIG. 9A shows a foundry p-cell layout of an NMOS transistor operating asa switch according to an embodiment of the present invention. FIG. 9Bshows a customized layout of an NMOS transistor operating as a switchaccording to an embodiment of the present invention. An NMOS transistorwith the following dimensions: W=108 μm, L=0.13 μm, fingers=6. Thedrain-source distance of the customized layout of the NMOS transistor isapproximately 4 times that of the p-cell layout. FIG. 9C shows acomparison table of parasitic capacitances of an NMOS transistor incutoff region based on a foundry p-cell layout and a customized layoutaccording to an embodiment of the present invention. The accurate valuesof these parasitic capacitances can be extracted from post layoutsimulations. When the transistor is OFF, the customized layout providesbetter isolation.

The overall drain-source coupling capacitance can be written as

C _(OFF) =C _(ds)+(C _(gs) ·C _(gd) /C _(gs) +C _(gd))  (2)

It is shown that C_(OFF) is reduced significantly from 45.5-fF for thestandard layout to 9.5-fF for the customized layout, which directlyprovides better isolation when the switch is used as the seriestransistor and is OFF. Furthermore, when this transistor is used as theshunt transistor, the smaller C_(OFF) leads to smaller loss, which posespositive effect on the overall insertion loss.

In the conventional series-shunt type single-ended T/R switcharrangement as shown in FIG. 6, the shunt transistors or shunt arm hasto provide sufficient large impedance when it is turned OFF, so thatinsertion loss can be prevented from severe degradation. At highfrequencies, the capacitive coupling effect becomes significant, leadingto a shunt path with lower impedance and thus higher loss. At the sametime, the presence of shunt arm degrades the power handling capabilityas the unintentional turn ON of the shunt transistor increases losssignificantly. Thus, when the isolation can be maintained withcustomized layout strategy, the shunt arm becomes not necessary and canbe removed to improve the insertion loss and linearity performances.FIG. 10 shows a graph of simulated insertion loss and isolation of a T/Rswitch with and without shunt arms according to an embodiment of thepresent invention. The results are obtained from post-layoutsimulations. For the switch with shunt arms, the sizes of seriestransistors and shunt transistors are W=108 μm/L=0.13 μm/6-fingers andW=21 μm/L=0.13 μm/3-fingers, respectively. For the switch without shuntarm, the sizes of series transistors are W=108 μm/L=0.13 μm/6-fingers,respectively. The layout employs standard p-cells and the customizedlayout as shown in FIG. 9B is employed. In the simulations, the signalis biased at 0.5-V and the high and low control voltages are 2-V and0-V, respectively. It is shown that the customized switch layoutachieves 2-dB better isolation when compared with standard transistorlayout, and this result is obtained without shunt arms. Thus, theinsertion loss and isolation tradeoffs due to shunt transistors arerelaxed. Benefiting from the absence of shunt arms, significantimprovement of insertion loss at high frequencies can be observed. Thelinearity performance is also improved without shunt arms. At 10-GHz,19-dBm P_(1dB) is obtained for the switch without shunt arms, while only15-dBm P_(1dB) is obtained for the switch with shunt arms.

FIG. 11 shows a graph of simulated linearity of a T/R switch with andwithout shunt arms, and with different types of body-floating accordingto an embodiment of the present invention. As can be seen from FIG. 11,when input power increases, insertion loss drops due to linearitylimitations (that is the switch cannot handle very large signals). Whenthe insertion loss drops by 1-dB, the input power is noted as P_(1dB),which is used to measure the linearity. There may also be other mannersof measuring linearity in a T/R switch. The simulated linearityperformance with different switch configurations is at 10-GHz. Thedifferent switch configurations are namely, switch with shunt arm andwithout body-floating, switch without shunt arm and without bodyfloating, switch without shunt arm and with P-well floating only andswitch without shunt arm and with double-well floating. As discussedearlier, the presence of shunt arms decreases the linearity, only 15-dBmP_(1dB) is obtained for a switch with shunt arms and 19-dBm is obtainedfor that without shunt arms. Both results are simulated without bodyfloating. With a P-well-only floating resistor of 5-kΩ, the P_(1dB) isimproved to 22-dBm. Dramatic improvement of linearity is observed when asecond 5-kΩ resistor is used to further float the deep N-well. Withresistor body-floating for both P-well and deep N-well, 29-dBm P_(1dB)is obtained. These results exhibit the influence of junction diodes onthe linearity performance and the efficiency of double-Wellbody-floating.

Furthermore, the body-floating will certainly affect the insertion lossand isolation performances, especially when it is combined with theproposed custom layout scheme. For a switch transistor that is turnedon, the parasitic capacitances regarding body, C_(sb) and C_(db), willno longer affect the insertion less as they are now floated. Thus, thenegative effect of increased drain and source areas for a transistorwhich is in the ON state is eliminated. FIG. 12 shows a graph ofsimulated insertion loss and isolation of a T/R switch without shuntarms, and with and without body-floating according to an embodiment ofthe present invention. Note that double-well body-floating is used inthe comparison; both circuits use the proposed custom layout and have noshunt transistors. It is clear that the insertion loss is improved withbody-floating technique.

FIG. 13 shows a schematic of a differential T/R switch arrangementaccording to an embodiment of the present invention. The differentialT/R switch arrangement 176 includes transistors M1, M2, M3 and M4,resistors R_(G1), R_(G2), R_(G3), R_(G4) and an inverter 178.Transistors M1, M2, M3, and M4 perform the main switching function. Ahigh control voltage V_(ctr1) turns M1 and M3 on, which enables thedifferential path between the antenna (ANT) and receiver (RX).Similarly, the differential transmit path is turned on when the controlvoltage is low. The control voltage is biased through the respectiveresistors R_(G1), R_(G2), R_(G3), R_(G4) to reduce the effect due tocapacitive coupling around the gate of the OFF transistors. Thedifferential nature results in an improved power handling capabilitycomparing with single-ended configurations. From the power point ofview, a differential output scheme is able to handle twice thesingle-ended output power, that is, 3-dB higher P_(1dB) could beachieved in the proposed differential switch. As the power handlingcapability is the bottleneck of CMOS T/R switches, differentialarchitecture is of great advantage in current silicon technology.Furthermore, comparing with single-ended architecture, the differentialnature permits higher linearity, lower offset, makes it immune to powersupply variations and substrate noise. Therefore, differentialarchitecture is normally preferred in applications requiring highersignal quality. Exploring the design of integrated differential T/Rswitch is essential for transceiver front-ends with fully differentialarchitecture. In the final circuit, only four switch transistors areemployed, the transistor count in the proposed differential T/R switcharrangement 176 is exactly equal to that in single-ended switch as shownin FIG. 6 with shunt arms.

Experimental Results

The efficiency of the invented method was checked and proved byexperimental results of the fabricated IC chip. The final differentialT/R switch circuit was fabricated in a 1.2-V two-poly eight-metal0.13-μm triple-well CMOS technology. The cut off frequency f_(T) of NMOStransistor is over 90-GHz. FIG. 14 shows a die photograph 180 offabricated differential T/R switch according to an embodiment of thepresent invention. The active area of the switch is about 180 μm×50 μm.

The measurements are carried out on a wafer, using Cascade Microtech'sdifferential G-S-S-G probes. A four-port network analyzer was employedin the experiment, which avoids the complicated on-chip balun design fortestability. The control voltage is 2/0-V and the TX/RX nodes arerespectively biased at 0.5-V. FIG. 15 shows a graph of measuredinsertion loss and isolation for differential-mode small-signalsaccording to an embodiment of the present invention. Assuming that theinput and output is matched, the scattering-parameter (S-parameter) S21is equivalent to the insertion loss (when switch is turned on) orisolation (when switch is turned off). The insertion loss is within2.0-dB over DC to 20-GHz. At 0.9-, 5.8-, 10-, 15- and 20-GHz, theinsertion loss is 0.7-, 1.5-, 1.7-, 1.7- and 2.0-dB, respectively. Theisolation is below 21-dB at frequencies up to 20-GHz.

S-parameter is a measure of circuit or device characteristics. Dependingon the configuration and application, the result may have differentphysical meaning, for example common-mode rejection ratio (CMRR),insertion loss, isolation. The CMRR is measured by the forwardtransmission coefficient from the transmitted common-mode signal to thereceived differential-mode signal. FIG. 16 shows a graph of measuredcommon-mode rejection ratio in the ON and OFF mode of the differentialT/R switch according to an embodiment of the present invention. In theON mode, the common-mode rejection is better than 28.7-dB. In the OFFmode, it is better than 40-dB.

FIG. 17 shows a graph of power handling capability in terms of P_(1dB)at different frequencies according to an embodiment of the presentinvention. The P_(1dB) increases from about 24.6-dBm at about 1-GHz tillabout 30.2-dBm at about 8-GHz, and it remains at the level around 30-dBmat frequencies above 8-GHz. The power handling capability may improvesignificantly when comparing the double-well body floating techniquewith the single-well resistive body-floating.

The aforementioned description of the various embodiments has beenpresented for purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formdisclosed, and obviously many modifications and variations are possiblein light of the disclosed teaching. It is intended that the scope of theinvention be defined by the claims appended hereto.

1. A transistor arrangement comprising a triple well structure, thetriple well structure comprising a substrate of a first conductivitytype; a first well region of a second conductivity type formed withinthe substrate; a second well region of the first conductivity type beingseparated from the substrate by the first well region; a firsttransistor formed on or in the second well region, the first transistorcomprising a body terminal being connected to the second well region;and a second well region switch being connected to the body terminal ofthe first transistor wherein the body terminal of the first transistoris connected to a reference potential when the second well region switchis closed.
 2. The transistor arrangement of claim 1, further comprisinga controller being connected to a control terminal of the second wellregion switch and controlling the second well region switch to be openedwhen the first transistor is in the ON state and to be closed when thefirst transistor is in the OFF state.
 3. The transistor arrangement ofclaim 1, the substrate being a P-type substrate.
 4. The transistorarrangement of claim 3, the first well region being an N-type wellregion.
 5. The transistor arrangement of claim 4, the second well regionbeing a P-type well region.
 6. The transistor arrangement of claim 1,the first transistor further comprising a source terminal, a gateterminal and a drain terminal.
 7. The transistor arrangement of claim 6,the source terminal comprising a source diffusion region of the secondconductivity type being formed in the second well region; the drainterminal comprising a drain diffusion region of the second conductivitytype being formed in the second well region.
 8. The transistorarrangement of claim 1, the body terminal comprising a body diffusionregion of the first conductivity type being formed in the second wellregion.
 9. The transistor arrangement of claim 1, the second well regionswitch being a second transistor.
 10. The transistor arrangement ofclaim 9, the second transistor being a field-effect transistor or abipolar transistor.
 11. The transistor arrangement of claim 9, thesecond transistor being selected from a group of transistors consistingof metal-oxide-semiconductor field-effect transistor, n-channelmetal-oxide-semiconductor field-effect transistor, p-channelmetal-oxide-semiconductor field-effect transistor, junction gatefield-effect transistor, insulated gate bipolar transistor.
 12. Thetransistor arrangement of claim 1, further comprising a first wellregion terminal connected to the first well region.
 13. The transistorarrangement of claim 12, the first well region terminal connected to thefirst well region comprising a diffusion region of the secondconductivity type being formed in the first well region.
 14. Thetransistor arrangement of claim 12, further comprising a passivecomponent being coupled to the first well region terminal.
 15. Thetransistor arrangement of claim 14, the passive component comprising acomponent selected from the group consisting of resistor, inductor andcapacitor.
 16. The transistor arrangement of claim 12, a first wellregion switch being coupled to the first well region terminal.
 17. Thetransistor arrangement of claim 16, the first well region switch being athird transistor.
 18. The transistor arrangement of claim 17, the thirdtransistor being a field-effect transistor or a bipolar transistor. 19.The transistor arrangement of claim 17, the third transistor beingselected from a group of transistors consisting ofmetal-oxide-semiconductor field-effect transistor, n-channelmetal-oxide-semiconductor field-effect transistor, p-channelmetal-oxide-semiconductor field-effect transistor, junction gatefield-effect transistor, insulated gate bipolar transistor.
 20. Thetransistor arrangement of claim 1, having a single-ended architecture.21. The transistor arrangement of claim 1, having a differentialarchitecture.
 22. The transistor arrangement of claim 1, a fourthtransistor having a source terminal, a gate terminal and a drainterminal.
 23. The transistor arrangement of claim 22, the gate terminalof the first transistor and the gate terminal of the fourth transistorbeing arranged at a distance from one another of at least about twicethe maximum process technology resolution.
 24. (canceled)
 25. (canceled)